Probability-based error adjustment and area-efficient approximate 4-2 compressor for approximate multiplier
Department of Electronics and Communication Engineering, Usharama College of Engineering and Technology, Andhra Pradesh, India.
Review
World Journal of Advanced Engineering Technology and Sciences, 2024, 11(02), 429–436.
Article DOI: 10.30574/wjaets.2024.11.2.0134
Publication history:
Received on 03 March 2024; revised on 10 April 2024; accepted on 13 April 2024
Abstract:
For error-tolerant applications like image processing, many multipliers based on approximation compressors have been created to save power; however, the combination of these multipliers has not been well researched. This short builds a hybrid multiplier based on the compressors, a constant approximation, and an AND gate for error correction. It also suggests a novel 4 gate 4-2 approximate compressor that is complementary with other compressors from previous work. The simulation results show that, in comparison to the exact multiplier, the proposed hybrid approximation multiplier has superior accuracy and electrical performance tradeoff, reducing the power-delay-area product (PDAP) by 66% with an MRED of 2.5%.
Keywords:
Partial products; Error correction; Approximate computing; 4-2 compressor; Digital multiplier; Compressor combination; Error compensation
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